Pixel structure and display panel

ABSTRACT

The present disclosure illustrates a pixel structure and a display panel. The pixel structure includes a plurality of data lines spaced apart from each other and electrically connected to a source driver; a plurality of scan lines spaced apart from each other and crossing the plurality of data lines, respectively, to form a plurality of pixel areas; at least one the connection line disposed in parallel with the plurality of data lines and electrically connected to the gate driver, and in each pixel at least one connection line is electrically connected to the scan line corresponding thereto.

BACKGROUND OF THE INVENTION 1. Field of the Invention

The present disclosure relates to a display technology field, more particularly to a pixel structure and a display panel.

2. Description of the Related Art

In recent years, with progress of technology, many different display devices (such as LCD display device or EL display device) are provided with flat-panel displays. Most LCD devices are backlight-type LCD devices, and the backlight-type LCD device includes a LCD panel and a backlight module. The LCD panel includes two transparent substrates, and liquid crystal sealed between the two transparent substrates.

The active switch array substrate of the existing LCD panel includes a source driver, a gate driver, a plurality of data lines and a plurality of scan lines. The source driver is electrically connected to the data lines, and the gate driver is electrically connected to the scan lines. The plurality of scan lines and the plurality of data lines are arranged on the active switch array substrate and cross to each other. The source driver is disposed at an end of the active switch array substrate, and the gate driver is disposed at a side of two sides of the active switch array substrate. However, the existing LCD panel is not easy to implement a narrow frame product.

SUMMARY OF THE INVENTION

In order to solve above-mentioned problem, the present disclosure provides a pixel structure and a display panel to implement a narrow frame product.

An objective of the present disclosure can be achieved by following technical solutions.

According to an aspect of the present disclosure, the present disclosure provides a pixel structure, the pixel structure includes: a plurality of data lines spaced apart from each other and electrically connected to a source driver; a plurality of scan lines spaced apart from each other and crossing the plurality of data lines, respectively, to form a plurality of pixel areas; at least one the connection line disposed in parallel with the plurality of data lines and electrically connected to the gate driver, and in each pixel at least one connection line is electrically connected to the scan line corresponding thereto.

In some embodiments, the pixel structure includes a plurality of active switches, and in each of the plurality of pixel areas, the plurality of connection lines are electrically connected to the plurality of scan lines, respectively.

In some embodiments, the pixel structure is formed on an active switch array substrate of a display panel, and the display panel can be a LCD panel, an organic light-emitting diode display panel, LED display panel, Plasmon display panel, field emission display panel, carbon nanotube display panel, or E-ink display panel.

According to an aspect of the present disclosure, the present disclosure provides a display panel, and the display panel includes: an active switch array substrate; a color filter substrate disposed opposite to the active switch array substrate; and a liquid crystal layer formed between the active switch array substrate and the color filter substrate. The active switch array substrate includes: a source driver disposed on the active switch array substrate; a gate driver disposed on the active switch array substrate, and the source driver and the gate driver disposed in the same direction on the active switch array substrate; a plurality of data lines spaced apart from each other and electrically connected to a source driver; a plurality of scan lines spaced apart from each other and crossing the plurality of data lines, respectively, to form a plurality of pixel areas; a plurality of connection lines spaced apart from each other and electrically connected to a gate driver. In each of the plurality of pixel areas, the at least one the connection line is electrically connected to one of the plurality of scan lines.

Preferably, lengths of the plurality of connection lines are gradually increased from a first side of the active switch array substrate to a second side of the active switch array substrate, the plurality of connection lines are electrically connected to the plurality of scan lines, in sequential order, through the first side of the active switch array substrate, and the first side is opposite to the second side.

Preferably, the active switch array substrate includes a first conductive layer and a second conductive layer; the plurality of scan lines are disposed in the first conductive layer; the plurality of connection lines are disposed in the second conductive layer; a conductive via is formed at a location where one of the plurality of connection lines crosses one of the plurality of scan lines corresponding thereto; the plurality of connection lines are electrically connected to the plurality of scan lines corresponding thereto, through the conductive vias, respectively.

In some embodiments, lengths of the plurality of connection lines are gradually increased from a first side of the active switch array substrate to a second side of the active switch array substrate, and the plurality of connection lines are electrically connected to the plurality of scan lines, in sequential order, through the first side of the active switch array substrate, and the first side is opposite to the second side. The lengths of the plurality of connection lines are gradually increased from the first side of the active switch array substrate to the second side of the active switch array substrate opposite to the first side, and the connection lines are electrically connected to the plurality of scan lines, in sequential order, from the first side to the second side, so as to facilitate to production. As a result, the active switch array substrate can have a compact layout.

In some embodiments, the plurality of connection lines are disposed in parallel with each other. The plurality of connection lines are disposed in parallel with each other, the plurality of connection lines are disposed in the same layer of the active switch array substrate, so as to facilitate to arrange lines. As a result, the active switch array substrate can have more compact layout.

In some embodiments, a plurality of connection lines and a plurality of data lines are disposed in parallel with each other. Preferably, the plurality of connection lines and the plurality of data lines can be disposed in parallel with each other, respectively, the connection lines and the data lines can be disposed on the same layer of the active switch array substrate, so as to facilitate to arrange lines. As a result, the active switch array substrate can have more compact layout.

In some embodiments, the active switch array substrate includes a first conductive layer and a second conductive layer; the plurality of scan lines are disposed in the first conductive layer; the plurality of connection lines are disposed in the second conductive layer; a conductive via is formed at a location where one of the plurality of connection lines crosses one of the plurality of scan lines corresponding thereto; the plurality of connection lines are electrically connected to the plurality of scan lines corresponding thereto, through the conductive vias, respectively. The scan lines and the connection lines are disposed in the first conductive layer and the second conductive layer of the display panel, respectively, so that the scan lines and the connection lines can be separated from to each other, and the scan lines and the connection lines are in communication with each other through the conductive vias at corresponding positions only, thereby preventing disorder in line arrangement of the scan lines and the data lines.

In some embodiments, each of the plurality of connection lines is disposed between two adjacent the data lines, and each connection line and each data line are disposed separately, to prevent the connection line and the data line from overlapping with each other, so as to prevent the connection line and the data line from overlapping with each other to form parasitic capacitance.

In some embodiments, the data lines includes a first data line and a second data line adjacent to each other, the connection lines includes a first connection line, the scan lines comprises a first scan lines, the active switch array substrate includes a first active switch and a first pixel, the first active switch is coupled to the first scan line, the first data line and the first pixel, respectively; the first active switch and the first pixel are disposed between the first data line and the second data line, the first connection line is electrically connected to the first scan line. The first connection line is disposed between the first pixel and the second data line, to prevent the first connection line from being disposed in the first pixel to affect normal function of the first pixel.

In some embodiments, the vertical shift register circuit of the gate driver is disposed at the first end of the active switch array substrate, so as to facilitate to electrically connect the vertical shift register circuit to the connection line.

In some embodiments, the pin of the source driver is bonded to an edge of the active switch array substrate.

In some embodiments, a length of the gate driver is shorter than or equal to a width of the display area of the display panel. The length of the gate driver is shorter than or equal to the width of the display area of display panel, so that the display panel can be more suitable for the narrow frame product.

In some embodiments, the gate driver is disposed at the top of the active switch array substrate, and the source driver is at the bottom of the active switch array substrate, but the way of disposing the gate driver and source driver is not limited thereto; for example, the source driver can also be disposed at the top of the active switch array substrate, and the gate driver is disposed at the bottom of the active switch array substrate.

According to other embodiment, the present disclosure further provides a display device including a backlight module and above-mentioned display panel.

In the display panel of the present disclosure, the source driver and the gate driver are disposed at the first end and the second end of the active switch array substrate opposite to each other, the source driver is electrically connected to the data line, and the gate driver is electrically connected to the scan lines through the connection lines, each connection line is electrically connected to a scan line corresponding thereto, so that the gate driver can normally drive the scan lines through the connection lines. In the present disclosure, the gate driver is disposed opposite to the source driver, so the gate driver does not occupy the spaces at sides of the active switch array substrate, so as to facilitate to implement the narrow frame display panel or frameless display panel.

BRIEF DESCRIPTION OF THE DRAWINGS

The structure, operating principle and effects of the present disclosure will be described in detail by way of various embodiments which are illustrated in the accompanying drawings.

FIG. 1 is a schematic structural view of a display panel of an embodiment of the present disclosure.

FIG. 2 is a schematic structural view of a part of a display panel of an embodiment of the present disclosure.

FIG. 3 is a schematic structural view of a part of a display panel of an embodiment of the present disclosure.

FIG. 4 is an equivalent circuit diagram of FIG. 2.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The following embodiments of the present disclosure are herein described in detail with reference to the accompanying drawings. These drawings show specific examples of the embodiments of the present disclosure. It is to be understood that these embodiments are exemplary implementations and are not to be construed as limiting the scope of the present disclosure in any way. Further modifications to the disclosed embodiments, as well as other embodiments, are also included within the scope of the appended claims. These embodiments are provided so that this disclosure is thorough and complete, and fully conveys the inventive concept to those skilled in the art. Regarding the drawings, the relative proportions and ratios of elements in the drawings may be exaggerated or diminished in size for the sake of clarity and convenience. Such arbitrary proportions are only illustrative and not limiting in any way. The same reference numbers are used in the drawings and description to refer to the same or like parts.

It is to be understood that, although the terms ‘first’, ‘second’, ‘third’, and so on, may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only for the purpose of distinguishing one component from another component. Thus, a first element discussed herein could be termed a second element without altering the description of the present disclosure. As used herein, the term “or” includes any and all combinations of one or more of the associated listed items.

It will be understood that when a component is referred to as being “on”, “connected to”, “coupled to”, or “adjacent to” another component, it can be directly on, connected to, electrically connected to, mechanically connected to, coupled to, or adjacent to the other component, or intervening components may also be present. It will also be understood that when a component is referred to as being “between” two components, it can be the only component between the two components, or one or more intervening components may also be present.

It will be understood that, although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section described below could be termed a second element, component, region, layer or section, without departing from the spirit and scope of the present invention.

The following refers to FIGS. 1 to 5 to describe a pixel structure, a display panel and a display device of embodiments of the present disclosure.

The following describes embodiments of the present disclosure in cooperation with FIGS. 1 to 5.

As shown in FIGS. 1-4, in an embodiment of the present disclosure, FIG. 1 shows a schematic structural view of a display panel of an embodiment of the present disclosure, FIG. 2 is a schematic structural view of a part of a display panel of an embodiment of the present disclosure, that is, FIG. 2 is a schematic structural view of a part of FIG. 1. Particularly, FIG. 2 is a schematic view of a pixel structure of the display panel. FIG. 3 is a schematic view of a part of a display panel of an embodiment of the present disclosure, FIG. 4 is a circuit diagram of an embodiment of the present disclosure, and is an equivalent circuit diagram of FIG. 2 particularly. In this embodiment, the display panel includes an active switch array substrate 100, and the active switch array substrate 100 includes a source driver 112, a gate driver 111, a plurality of data lines 113 spaced apart from each other, a plurality of scan lines 114 spaced apart from each other, and a plurality of connection lines 115 spaced apart from each other.

The source driver 112 is disposed at a first end 101 of the active switch array substrate 100; the gate driver 111 is disposed at a second end 102 of the active switch array substrate 100, and the second end 102 is opposite to the first end 101, in other words, the second end 102 is other end of the active switch array substrate 100 opposite to the first end 101. The plurality of data lines 113 is electrically connected to a source driver 112. The plurality of scan lines 114 cross the plurality of data lines 113, respectively. The plurality of connection lines 115 are electrically connected to a gate driver 111, and each the connection line 115 is electrically connected to a scan line 114 corresponding thereto.

According to the embodiment of the present disclosure, in the display panel, the source driver 112 and the gate driver 111 are disposed at the first end 101 and the second end 102 of the active switch array substrate 100 opposite to each other, the source driver 112 is electrically connected to the data line 113, the gate driver 111 is electrically connected to the scan lines 114 through the connection lines 115, and each the connection line 115 is electrically connected to a scan line 114 corresponding thereto. As a result, the gate driver 111 can normally drive the scan lines 114 through the connection lines 115. In the embodiment of the present disclosure, the gate driver 111 is disposed to the end opposite to the source driver 112, and does not occupy the spaces at sides of the active switch array substrate 100, so that the narrow frame the display panel or frameless the display panel can be implement more easily.

Lengths of the plurality of connection lines 115 are gradually increased from a first side 103 of the active switch array substrate 100 to a s second side 104 of the active switch array substrate 100, and the plurality of connection lines 115 are electrically connected to the plurality of scan lines 114, in sequential order, through the first side 103 of the active switch array substrate 100; the first side 103 is opposite to the second side 104, that is, the first side 103 is other side of the active switch array substrate 100 opposite to the second side 104. The lengths of the plurality of connection lines 115 are gradually increased from the first side 103 of the active switch array substrate 100 to the second side 104 of the active switch array substrate 100 opposite to the first side 103, and the connection lines are electrically connected to the plurality of scan lines 114, in sequential order, from the first side 103 to the second side 104, so that production can be easily and the active switch array substrate can have a compact layout. However, it is to be noted that, the layout of the connection lines is not limited to above-mentioned example; for example, the lengths of the connection lines can be gradually increased from the second side of the active switch array substrate to the first side of the active switch array substrate; in another example, the connection lines have the same length, and are electrically connected to the scan lines only at the predetermined connection positions.

Furthermore, the plurality of connection lines 115 are disposed in parallel with each other. The plurality of connection lines 115 are disposed in parallel with each other, the plurality of connection lines 115 are disposed in the same layer of the active switch array substrate, so that line arrangement can be easier and the active switch array substrate 100 can have more compact layout. However, it is to be noted that, the connection lines can be disposed in non-parallel with each other, in other embodiment.

Furthermore, the plurality of connection lines 115 and the plurality of data lines 113 are disposed in parallel with each other. In the embodiment of the present disclosure, the plurality of connection lines 115 and the plurality of data lines 113 are disposed in parallel with each other, the connection lines 115 and the data lines 113 can be disposed on the same layer of the active switch array substrate 100, so that line arrangement can be easier and the active switch array substrate 100 can have more compact layout.

As shown in FIG. 4, the display panel comprises a first conductive layer 120 and a second conductive layer 130, the plurality of scan lines 114 are disposed in the first conductive layer, the plurality of connection lines 115 are disposed in the second conductive layer 130, a conductive via 131 is formed at a location where each of the plurality of connection lines 115 crosses each of the plurality of scan lines 114 corresponding thereto, and the plurality of connection lines 115 are electrically connected to the plurality of scan lines 114 corresponding thereto, through the conductive via 131 s, respectively. The scan lines 114 and the connection lines 115 are disposed in the first conductive layer 120 and the second conductive layer 130 of the display panel, respectively, so that the scan lines 114 and the connection lines 115 are separated from to each other, the scan lines 114 and the connection lines 115 are in communication with each other through the conductive via 131 s at corresponding positions only, so as to prevent disorder in line arrangement of the scan lines 114 and the connection lines 115.

Each of the plurality of connection lines 115 is disposed between two adjacent the data lines 113, and each the connection line and each the data line are disposed separately, to prevent the connection line and the data line from overlapping with each other, so as to further prevent the connection line and the data line from overlapping with each other to form parasitic capacitance.

As shown FIGS. 3 and 5, in a pixel structure, the data lines 113 comprises a first data line 1131 and a second data line 1132 adjacent to each other, the connection line 115 comprises a first connection line 1151, the scan line 114 comprises a first scan line 1141 and a second scan line 1142, the active switch array substrate 100 comprises a first active switch 117 and a first pixel 1161. The first active switch 117 is coupled to the first scan line 1141, the first data line 1131 and the first pixel 1161, respectively. The first active switch 117 and the first pixel 1161 are disposed between the first data line 1131 and the second data line 1132, the first connection line 1151 is electrically connected to the first scan line 1141, the first connection line 1151 is disposed between the first pixel 1161 and the second data line 1132. The second data line 1132 is a data line next to the first data line 1131, and the second scan line 1142 is a scan line previous to the first scan line 1141. In the embodiment of the present disclosure, the first connection line 1151 is disposed between the first pixel 1161 and the second data line 1132, to prevent the first connection line 1151 from being disposed in the first pixel 1161 to affect normal function of the first pixel 1161. It is to be noted that, FIG. 3 just shows the structure of a pixel of the display panel, and structures of other pixels of the display panel are similar to the structure shown in FIG. 3, so their detailed descriptions are not repeated.

The active switch array substrate 100 comprises a plurality of common line 118, the connection line 115 covers on the common line 118. Particularly, as shown in FIG. 3, the first connection line 1151 covers on the common line 118.

In this embodiment, the first active switch 117 is coupled to the common line 118, and a pixel capacitor Clc and a storage capacitor Cst are disposed between the first active switch 117 and the common line 118, to normally drive the display panel.

In this embodiment, the gate driver comprises a vertical shift register circuit disposed at a first end of the active switch array substrate, so as to facilitate to electrically connect the vertical shift register circuit to the connection line.

In this embodiment, the pin of the source driver is bonded to an edge of the active switch array substrate.

In this embodiment, the length of the gate driver 111 is shorter than or equal to a width of the display area 116 of the display panel. When the length of the gate driver 111 is shorter than or equal to the width of the display area 116 of the display panel, the display panel can be more suitable for the narrow frame product. Preferably, the length of the gate driver 111 can be equal to the width of the display area 116, and it is to be noted that, in other embodiment, the length of the gate driver 111 can also be slightly longer than the display area.

The gate driver 111 is disposed at the top of the active switch array substrate 100, and the source driver 112 is at the bottom of the active switch array substrate 100. The way of disposing the gate driver and the source driver is not limited to above-mentioned example, and the source driver can also be disposed at the top of the active switch array substrate, the gate driver is disposed at the bottom of the active switch array substrate, in other embodiment.

In this embodiment, the display panel comprises a plurality of CF substrates, and the CF substrate and the active switch array substrate are disposed opposite to each other.

As shown in FIG. 5, in some embodiments, each pixel structure 1162 on the active switch array substrate can include a plurality of active switches 1171 and 1172, for example, two TFTs. In each of the plurality of pixel structure 1162 s, the plurality of connection lines 115 can electrically connected to the plurality of scan lines 114, respectively, so as to electrically connect to the plurality of active switches 1171 and 1172 corresponding thereto.

In some embodiments, the pixel structure can be formed on the active switch array substrate of the display panel; preferably, the display panel can be LCD panel, OLED display panel, LED display panel, Plasmon display panel, field emission display panel, carbon nanotube display panel or E-ink display panel,

The present disclosure disclosed herein has been described by means of specific embodiments. However, numerous modifications, variations and enhancements can be made thereto by those skilled in the art without departing from the spirit and scope of the disclosure set forth in the claims. 

What is claimed is:
 1. A pixel structure, comprising: a plurality of data lines spaced apart from each other, wherein the plurality of data lines are electrically connected to a source driver; a plurality of scan lines spaced apart from each other, wherein the plurality of scan lines crossing the plurality of data lines, respectively, to form a plurality of pixel areas; and at least one connection line disposed in parallel with the plurality of data lines and electrically connected to a gate driver, wherein in each of the plurality of pixel areas, the at least one connection line is electrically connected to at least one of the plurality of scan lines.
 2. The pixel structure according to claim 1, wherein the pixel structure comprises a plurality of active switches, and the plurality of connection lines are electrically connected to the plurality of scan lines respectively, in each of the plurality of pixel areas.
 3. A pixel structure, comprising: a plurality of data lines spaced apart from each other, wherein the plurality of data lines electrically connected to a source driver; a plurality of scan lines spaced apart from each other, wherein the plurality of scan lines crossing the plurality of data lines, respectively, to form a plurality of pixel areas; and a plurality of connection lines disposed in parallel with the plurality of data lines and electrically connected to a gate driver; wherein the pixel structure comprises a plurality of active switches, and in each of the plurality of pixel areas, the plurality of connection lines are electrically connected to the plurality of scan lines, respectively; wherein the pixel structure is formed on an active switch array substrate of a display panel.
 4. A display panel, comprising: an active switch array substrate; an color filter substrate disposed opposite to the active switch array substrate; and an liquid crystal layer formed between the active switch array substrate and the color filter substrate; wherein the active switch array substrate comprises: a source driver disposed on the active switch array substrate; a gate driver disposed on the active switch array substrate, wherein the source driver and the gate driver are disposed in the same direction on the active switch array substrate; a plurality of data lines spaced apart from each other and electrically connected to the source driver; a plurality of scan lines spaced apart from each other and crossing the plurality of data lines, respectively, to form a plurality of pixel areas; and a plurality of connection lines spaced apart from each other and electrically connected to the gate driver, wherein in each of the plurality of pixel areas, at least one of the plurality of connection lines is electrically connected to at least one of the plurality of scan lines; wherein lengths of the plurality of connection lines are gradually increased from a first side of the active switch array substrate to a second side of the active switch array substrate, and the plurality of connection lines are electrically connected to the plurality of scan lines, in sequential order, through the first side of the active switch array substrate, the first side is opposite to the second side; wherein the active switch array substrate comprises a first conductive layer and a second conductive layer, the plurality of scan lines are disposed in the first conductive layer, the plurality of connection lines are disposed in the second conductive layer, conductive vias are formed at each location where one of the plurality of connection lines crosses one of the plurality of scan lines corresponding thereto, and the plurality of connection lines are electrically connected to the plurality of scan lines corresponding thereto, through the conductive vias, respectively.
 5. The display panel according to claim 4, wherein the source driver is disposed at a first end of the active switch array substrate, the gate driver is disposed at a second end of the active switch array substrate, and the second end is opposite to the first end.
 6. The display panel according to claim 4, wherein a plurality of connection lines are disposed in parallel with each other.
 7. The display panel according to claim 4, wherein the plurality of connection lines and the plurality of data lines are disposed in parallel with each other.
 8. The display panel according to claim 4, wherein each of the plurality of connection lines is disposed between two adjacent data lines.
 9. The display panel according to claim 4, wherein a plurality of connection lines are disposed in parallel with each other; wherein the plurality of connection lines and the plurality of data lines are disposed in parallel with each other; wherein each of the plurality of connection lines is disposed between two adjacent data lines.
 10. The display panel according to claim 4, wherein the plurality of data lines comprise a first data line and a second data line adjacent to each other, the plurality of connection line comprises a first connection line, the plurality of scan lines comprises a first scan line, the active switch array substrate comprises a first active switch and a first pixel, the first active switch is coupled to the first scan line, the first data line and the first pixel, the first active switch and the first pixel are disposed between the first data line and the second data line, the first connection line is electrically connected to the first scan line, the first connection line is disposed between the first pixel and the second data line.
 11. The display panel according to claim 4, wherein the active switch array substrate comprises a plurality of common lines, and the plurality of connection lines cover on the plurality of common lines.
 12. The display panel according to claim 4, wherein the active switch array substrate comprises a first active switch and a common line, the first active switch is coupled to the common line, and a pixel capacitor and a storage capacitor are formed between the first active switch and the common line.
 13. The display panel according to claim 5, wherein the gate driver comprises a vertical shift register circuit, and the vertical shift register circuit is disposed at the first end of the active switch array substrate.
 14. The display panel according to claim 4, wherein the source driver is disposed at a first end of the active switch array substrate, the gate driver is disposed at a second end of the active switch array substrate, and the second end is opposite to the first end; wherein the gate driver comprises a vertical shift register circuit disposed at the first end of the active switch array substrate.
 15. The display panel according to claim 4, wherein a pin of the source driver is bonded to an edge of the active switch array substrate.
 16. The display panel according to claim 4, wherein a length of the gate driver is shorter than or equal to a width of the display area of the display panel.
 17. The display panel according to claim 4, wherein the gate driver is disposed at the top of the active switch array substrate, and the source driver is at the bottom of the active switch array substrate. 